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| Sr. Design Verification Engineer41202 | |
| Posting Date: | 11/14/08 |
| Type: | Permanent |
| Description: | Verify hardware design IP functionality from test plan to RTL signoff
Design and implement the next-generation PCIe verification architecture using SystemVerilog Create test plans and execute portions or all of test plans for the design IP Develop and manage simulation regression environment for design IP For immediate confidential consideration, please apply online today! |
| Start Date: | ASAP |
| Required Skills: | 3+ years experience with design verification using any EDA tools (example SystemVerilog,SystemC), Perl or Python scripting experience
Experience creating new designs from an "idea" DESIRED Experience with PCI-Express (including Gen2, IO Virtualization) or related protocols |
| Education: | BS/MS EE
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| Contact |
| APPLY ONLINE |